The present invention relates to microwave synthesizers, and more particularly, to a microwave synthesizer that requires fewer phase-lock loops for a given phase noise requirement.
Microwave synthesizers are commonly used in test equipment to provide a test signal that sweeps a frequency range specified by the user. A microwave synthesizer can be designed using several approaches, depending on the performance requirements. The lowest cost approach utilizes a single phase-lock loop (PLL) design. In a single loop design, the output of the synthesizer is divided by a divider and compared against a reference frequency. Denote the division factor by Fdiv. When the loop is locked, the output frequency of the synthesizer is Fdiv times the reference frequency. For every 1 Hz of frequency noise at the reference frequency, the output of the synthesizer has Fdiv Hz of frequency noise. The noise gain of the PLL is thus Fdiv; hence, Fdiv needs to be as small as possible to minimize noise. However, if one attempts to minimize Fdiv by utilizing a large reference frequency, the output frequency resolution is reduced.
To overcome these conflicting requirements a Multiple-Modulator Fractional-N Divider (FND) is often utilized. An FND provides a division factor that is not restricted to integers. Denote the division factor by N.F, where F is the fractional part of the divisor. The minimum resolution is now determined by the amount that F can be incremented. Accordingly, smaller division factors can be utilized thereby reducing the noise gain.
Unfortunately, currently available Multiple-Modulator FNDs are inherently limited in the range of division factors they provide since the fractional division is implemented by hopping among the adjacent integer division factors to achieve the average N.F value. In particular, dividers that provide division factors less than about 10 can not be implemented due to the large disturbance to the loop that occurs with each hop. For a FND implemented with K modulators, to achieve the average division factor of N.F, the actual integer divider factor is varied between Nxe2x88x92K to N+K+1. If 3 modulators are used to produce a division factor of 10.3, for example, the actual integer division values would vary between 7 to 14 and the maximum output frequency of the FND would be 100% greater than minimum output frequency. If N.F is 60.3, the maximum frequency would only be 64/57, or 12% higher than the minimum output frequency. The PLL can tolerate a small amount of frequency jitter. If larger frequency jitter is present, the PLL has difficulty locking and increased noise also becomes a problem. Accordingly, a large N.F value provides the best performance with respect to frequency division, and a small N.F provides the smallest noise gain. In addition, the output frequency of commercially available FNDs is limited to about 50 MHz. Hence, there is a lower limit on the noise gain that can be obtained using prior art FND PLL designs.
Broadly, it is the object of the present invention to provide an improved microwave frequency synthesizer.
It is a further object of the present invention to provide a microwave synthesizer that achieves the high resolution characterized by FND designs while providing reduced noise gain.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
The present invention is a frequency synthesizer that includes an output oscillator, a difference circuit, a reference circuit, a feedback circuit and a comparator. The output oscillator generates an output signal whose frequency, FOUT, is determined by an oscillator input signal. The difference circuit generates a signal having a frequency, Fsif=FOUTxe2x88x92FOFFSET. The reference circuit generates a reference signal having a frequency Fref. The reference circuit includes a reference oscillator for generating a reference oscillator output signal having a frequency F1 and a first division circuit for generating a signal having a frequency equal to F1 divided by R. The feedback circuit generates a feedback signal having an output frequency, Ffb, from the input signal Fsif. The feedback signal generating circuit includes a second division circuit having a division factor chosen such that Fsif/Ffb less than 10 to minimize the noise gain. The comparator compares the reference signal and the feedback signal and generates the oscillator control signal. One of the first and second division circuits is a Fractional-N Divider having a division factor, N.F, greater than 10. If the second division circuit is the Fractional-N Divider, the feedback circuit includes a multiplication circuit for generating a multiplied signal having a frequency equal to X times Fsif, and the Fractional-N Divider generating the feedback signal from the multiplied signal. In the preferred embodiment of the present invention, the first division circuit is the Fractional-N Divider. In one embodiment of the invention, the input to the Factional-N Divider varies over time thereby causing the output oscillator to sweep through a corresponding frequency range.